1. Field of the Invention
The present invention relates to a dual port RAM (random access memory) capable of writing or reading data to or from the same memory from two independent ports, and more particularly to its self-test function.
2. Related Background Art
A dual port RAM has a memory block and two ports A and B. If a normal operation is specified by a mode signal MOD in the dual port RAM, the port A of the memory block is connected to a system bus of a first functional block and is given a first clock signal. The port B of the memory block is connected to a system bus of a second functional block B and is given a second clock signal. In addition, a self-test circuit connected to the memory block is disconnected by a selector.
On the other hand, if a test operation is specified by a mode signal, the port A and the port B of the memory block are disconnected from the first and second functional blocks by the selector and then connected to the self-test circuit. A first clock signal is supplied to the port A of the memory block and the self-test circuit. Furthermore, a first clock signal is supplied to the port B of the memory block via a selector.
If a test start signal is given to the self-test circuit in this condition, the self-test circuit tests data write/read processing to or from the memory block and then a test result is output. In this self test, data written from the port A is read from the port B for verification or conversely data written from the port B is read from the port A for verification. Since a single self-test circuit is used for controlling the port A and the port B of the memory block simultaneously, these ports A and B are given a common clock signal (the first clock signal) for the read/write processing.
The above dual port RAM, however, has the following problem. In the self-test, there is a need for supplying the same first clock signal as one for the port A to the port B. Therefore, the first and second clock signals are switched to each other by using the selector on a clock supplying path in the side of the port B. This causes a difference in timing between the first clock signal supplied to the port A and the first clock signal supplied to the port B, which disables a normal self-test particularly in a fast operation, thus causing a problem.
Furthermore, there is a problem that the dual port RAM is incapable of performing a self-test when the first and second clock signals at the port A and the port B are different from each other in speed.